DSεα♥​DAC1.0 is an audio DAC based o♦¥♠n DSD audio technology.&n ←bsp; It took five years€↓≠± to develop and realize★∑<÷d  the perfect playback ♣✘​×of DSD audio.  It has three ∏∑∏→advanced audio technologies.

    1: high-precision‌÷< DSD frequency up algorithm,

    2: synchronous direct c✔σ¶lock,

    3: clock ‍•Ωreplacement technology.λ>♠> 

        It is₽≠&↑ a perfect DSD audio DACπ♦φ↑.  DSDAC1.0 has three m∞∞←odels : standerd, super clock model ™γ↓ , deluxe model.

Difference between DSDAC1.0&±↔"×nbsp;standerd model and super clΩλ¶ock model  ← →;

1: The clock system of &↑ε₽←nbsp;super clock model has  ©higher performance, RMS jitter is as l<→₹♦ow as 100fs

2: Some advance component are used

1、 R & D background
 

      D↓₹≤SD audio coding mode is→≈  almost perfect alt<​φ↑hough it has many technic​✔ ∞al barriers.  The unique cε∞harm of  DSD sound  att&$Ωracts many people,  man↔←y music lovers have high enthuε siasm for DSD in the past decade. &nb♥≠±±sp;At present more than™§♣ 10000 SACD music albums have beλ✘‌↓en released in the world  ✘φΩwhich is a valuable music resource ‌↓for mankind.  In order to make i£↓¥±t play a greater role many peo₹✔‍ple are making unremi↕∏tting efforts  and we are one of t​>↕hem.
 

      Du♣☆λe to the disc storage space is limite< γd,  SACD adop∑£ ÷ts the dsd64 format which with lower®¥₩ frequency.  Th∏±e accuracy of dsd64 in DA conversi✔‌on is low and there is out of →δband noise (noise above 2♦α₽3khz) after  DA process. &n ¥↓bsp;Therefore, most SACD playe£™ γrs must convert dsd64≤∑∞ to PCM  before DA ¥£conversion. This way weak∏≈ens the advantages of DSD , and it∞∑<$ was an important reason why SACD δ₩fails in the competition with CD.

      &₹≈nbsp;With the passage of time ,&nb←'sp; more in-depth rese"↕arch on DSD coding t<≤echnology have made progress.&nb★∏>sp; FPGA technology has also made ♠♦‌great progress.  Ther≈≈$"efore the technology of raise DS±•D frequency form 2.8224MHz to high ↓×÷≤number has been available.&↓✔≥nbsp; It can make the DA proces ←s with higher accuracy $±₽after frequency  was ri≈±βsed .  At the same time becaus↓★♦e the frequency of ouδφδλt of  band noise is pushed u®≤£p , it can be easily f™εiltered out.  Based on th‍✘✘ese conditions we decided to st↔<art the research and development th¥ e algorithm for DSD frequency &nbs♣α→↓p;increasing .
 
 
 
 
2、 R & D history

     ★"  DSD technology is a₹↔ commercial technology,&‌δnbsp; so there is liδ‍γttle public informati×÷βon can be found.   ↓≈↓;After several years of ef±'forts , we studied the basic theory ¶≥of DSD and created a u♣± ♣nique algorithm to realize the ±↔♠high-precision frequency rising.>‍  At the same time &n>¥​bsp;we made a comprehensiv€₩σ≈e innovation in the cλ•÷lock  framework ,  crea✘↓≥εted two unique technologies of &≈★quot;synchronous direct★β clock" and "clock blocking​★©". 
 

      Analog circui €±∑t is the key part of DAC. The ad✘©γ vantages of the digitalε€ part must rely on the anal∞βπΩog circuit . One deviation δ₽of the analog part is enough to o"π∑↕ffset the three advantages of★♠↔$ the digital part. &n<∞bsp;The R & D team of DSDAC1×δβ×.0 spent nearly a year✔§ for designing the circuit arc♥✘∞®hitecture of the analog part mo✘↕re than 20 times.   Af≤"ter a long period of adjustment ，ds£σ↔dac1.0 has reached th¥↕​e level of reference DAC↔♦α
 
 

 
3、 Core technology
 

      &nα&₩bsp;The high-precision frequenc©$¥☆y rise algorithm  is the ₩♦core of  DSDAC1.0. ‌±  Although there are many ways  ‌βto realize frequency rising  ±∏;but the high-precision fr✔↓§®equency rise  algorithm is a comπ¥plex mathematical problem &n¥∑bsp;not a digital te¥α chnical problem.  Th≈™e technology of frequency risi™☆♥ng not only makes DSD m£₹®§ore widely used but also makes DSDA÷​₹C1.0 become leading aud↕₩δio DAC.
 

       Sy¶♣₹♣nchronous direct clock technology :∏π  femtosecond clock insid™<•e DSDAC1.0 will be sent to the shσ♦ift register directl λ₹✔y without any interme<εdiate conversion , so that₹↓ the performance of femt&π osecond clock is directly reflec←♣∑ted in the analog output.  This te®§chnology is different from ∏∑the use of external femtosecondφ€​™ clock and built-in femtosecond cry‌→stal oscillator.  The use of e​↕¶xternal clock and built-in crystal£¶®★ oscillator can only be ±>↑a source clock,  it must be divδ♠ided by frequency divider.  In thi•δs way,  there are large aπ✘₩dditive jitter which changes the femt™$osecond clock from femtosecond to p∞$‌♠icosecond.  The clock o♦✔f DSDAC1.0 can be sent t¥•₩o shift register&nbs€≤¥p;directly  without frδ ≈equency divider,  ★&♣it is advanced technλ☆ology of clock application .

       Cl≤€ock replacement.  &nb♥™↕©sp;It means that the cl₽→εock from the pre-devices is abaε♣™ndoned and the DSDAC1π™.0 only uses the local cloc >←k.  In this way, the cl±₹πλock of pre-devices such as•♦↓↕ digital turntable, CD player an₩♣®d digital interface will no l α∑onger affect the per↔≈¶≤formance of  DAC. φ≠☆≥; As long as the data is ε"correct,  there is no diffe×γ$εrence in any digital sour÷π₽ce.  This technolo<σgy is a dream of digital audio. φ✔÷α; Clock replacement  λ× is  synchronizatioδ©n process,  not the  "ASRC , which has great negative impacγ♥ t on sound quality.  <£®; It solves the clock pσ↓'↑roblem that has plagued the $¥‌digital audio field for ‌'→a long time.
 
 
        DS♦ DAC1.0 has advanced US®☆B interface and can receives&nbλ÷‍sp;DSD source code in nat ∑€≥ive mode.  As a DSD DAC ,&nbσσ✘sp; receives DSD source code ¥'↔is a necessary function∞∑↔.  DSDAC1.0 has two ways to inp ÷↕₹ut DSD source code:  one is to inpΩβ≤✔ut dsd64 via SP♥>≤‌DIF in DOP mode ,  and the✘β₽® other is to input dsd512 via★>  USB in native mode.  T ★he XU208 scheme of XMOS inside Dσ>©SDAC1.0 has ground isoαδlation function ,  the interferenc£φe of the front digital source c©↑↓an be almost  isolate∑ε®×.  We have custom§≠♠÷ized the special driver from​♥₩≥ XMOS to enable DS₽↔DAC1.0 to receive the source§δ code of dsd512 in native ↓♥≤♠mode.

Functional parameters

 
SPDIF sampling rate:  ♠™≈; PCM 192 kHz / dop64 (AES, optic‌≤±®al fiber, coaxial, BNC )
 
USB sampling rate:   pcm384 / ds→ ↑≥d512 (native)
 
Output interface:   on£$e for XLR and one for R♦Ω↕♣CA
 
Output level:   5.0V RMS (λ'XLR), 2.5V RMS (RCA)
 
Volume control range:   - 70dBφ ✔ ~ 0dB
 
Overall dimension:   430 * 360 &♦≥* 100mm
 
Net weight:  10.♣ 6kg
 
Gross weight:  13.3kgλ×φ÷